In today's semiconductor manufacturing industry, large-scale integrated circuit (LSI) devices continue to be developed at increased levels of integration and complexity. These increased levels of integration require minute and highly accurate LSI patterns to be developed and produced. These patterns require highly accurate pattern formation technologies for forming the minute pattern features. According to conventional technologies, semiconductor devices such as integrated circuits, are fabricated on a semiconductor substrate using a photomask set, each photomask used to form a complete exposure pattern at a particular device level. The exposure pattern is transferred onto the device using photolithography and other operations and may also be referred to as a device pattern. When the exposure pattern is formed in a masking layer such as photoresist, it is used as a mask for implantation, etching or any of various other processing operations that are carried out upon the semiconductor substrate to produce the device pattern. As device features continue to become more miniaturized and formed in closer proximity, and as the dimensions of the device features approach or become smaller than the wavelengths of the light used to expose the particular features, one approach has been to use DPL, double patterning lithography, to form the device pattern on the semiconductor substrate.
According to conventional methods, a design house provides a design layout of the exposure pattern typically in an electronic file, such as a file stored on a computer readable storage medium. The design layout may be generated using CAD, computer-aided design, techniques and the exposure pattern is provided to a mask foundry which manufactures photomasks according to the design layout. According to DPL techniques, the design layout is decomposed into two separate portions, each formed onto a separate photomask. The decomposition results in two photomasks and a pattern is formed in a layer of the semiconductor device by first performing a lithography operation using one photomask, then performing an etching or implantation or other operation upon the layer, then performing a second lithography operation using the other photomask and performing a separate etching or implantation or other operation upon the layer.
The design layout of the exposure pattern is conventionally provided by the design house to the mask foundry. The decomposition of the design layout is conventionally done by the foundry which decomposes the design layout into two design layouts based essentially only on minimum spacing design rules for the design layout at hand, and then produces the two masks from the two decomposed design layout patterns. A shortcoming of present DPL techniques is that the mask foundry does not take other factors into account when decomposing the masks. According to conventional techniques, when a particular design layout is used in conjunction with different devices or different processing technologies, or used in different device environments, these differences are not considered by the mask foundry when decomposing the design layout.
Present DPL techniques are therefore beset with various shortcomings and limitations.